The evolution of modern processor architectures, in conjunction with technology scaling, has produced processors with higher performance to meet today's increasing computational demands, and also helped make power efficiency one of the paramount design concerns and objectives for a wide spread of enterprise-class and embedded processors. In addition to saving energy, proper reduction of power consumption can lead to dramatic benefits in reducing thermal hot spots and the cost of chip-cooling. Researchers have been devoted to the optimization of processors, for example system-on-a-chip (SoC) processors, whose key to optimization is to operate at the most efficient frequency and voltage, depending on the workload requirements. As an example, power efficient optimization prefers the lowest voltage, since power is proportional to the square of voltage. On the other hand, optimization for the highest performance may require the highest frequencies possible. In both cases, it is important to run at the highest frequency within the given voltage.
To this end, dynamic voltage and frequency scaling (DVFS) has become a key avenue for achieving power efficiency via adjustment of the operating voltage and frequency of processors in runtimes for devices such as web servers, smartphones, tablet devices, laptops, and other devices. One central challenge in developing DVFS schemes is to balance two competing objectives: maximizing of power saving and achieving high performance based on workload demand. The latter is particularly critical for latency-sensitive applications that require a high degree of quality of service (QoS). Therefore, successfully achieving power efficiency realizes lower total energy consumption for the processors without sacrificing QoS from the perspective of the user.
In this respect, DVFS is an established technique for run-time selection of performance states, also referred to as P-states, at most optimal frequency and voltage point. However, the effectiveness of DVFS can be limited by the voltage range for operation, and the granularity of islands for independent voltage control.
The voltage range for DVFS optimization is traditionally limited by voltage margin requirements related to yield and reliability of the design. These limits are determined based on the worst case assumptions of product usage. For example, in static random access memory (SRAM), a nominal product minimum voltage and a nominal product maximum voltage are the minimum and maximum voltages, respectively, of a product-specified range of voltage levels, as specified by the manufacturer of the product, at which the voltage level for a functional unit is set during operation. Previous DVFS techniques use fine-grained voltage islands or dual voltage rail SRAM arrays. Fine-grained voltage islands, also known as “power islands”, allow for different functional units within a single SoC to operate at different voltage levels and frequencies that are independent of each other. Likewise, dual voltage rail SRAM arrays incorporate a different power supply voltage for each of the memory cells, or bit cells, and the logic circuits, or the peripheral circuits, so that the power supply voltage for the memory cells is maintained at a stable and operable level while the power supply voltage for the logic circuits can be reduced significantly, thereby increasing stability and performance. However, a need exists for an improved power control scheme.